Amplifier with variable signal gain and matched gain bandwidth

ABSTRACT

A sensor includes a gain stage with a differential amplifier with an adjustable gain. The differential amplifier may change its gain in response to the magnitude of a signal readout from the pixel array. The differential amplifier includes an input transistor with an adjustable transconductance. A transconductance controller can change the bias currents supplied to one or more sets of parallel transistors in the input transistor and consequently change the transconductance, and power consumption, of the input transistor. The transconductance controller can select a transconductance setting that is associated with a selected gain setting in order to more efficiently match the power consumption of the amplifier to its gain.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional ApplicationSerial No. 60/285,431 filed on Apr. 19, 2001.

BACKGROUND

[0002] Active pixel sensor (APS) imaging devices are described in U.S.Pat. No. 5,471,515. These imaging devices include an array of pixelcells, arranged in rows and columns, that convert light energy intoelectric signals. Each pixel includes a photodetector and one or moreactive transistors. The transistors typically provide amplification,readout control and reset control, in addition to producing the electricsignal output from the cell.

[0003] The pixels generate analog signals, which are converted intodigital signals by analog-to-digital converters (ADCs) for furtherprocessing. The analog signal read-out chain may include a gain stage toamplify the analog signals into a range suitable for the ADCs. Themagnitude of the gain may range from unity to about eight.

[0004] During readout, the amplifier provides adjustable signal gainwith a given amplifier accuracy. The amplifier accuracy determines therequired amplifier settling time, i.e., the interval between theapplication of the input voltage step and the point at which the outputsignal reaches and stays within a given error band.

[0005] In many sensors, the unity gain frequency of the amplifier isselected to satisfy the settling time requirement for the worst-casecondition, i.e., the maximum signal gain. While this design approachensures that the amplifier is complying with the settling timerequirement at any signal gain selection, it only optimizes theamplifier power consumption in the unique case of the worst-case(maximum) gain setting. For any gain setting lower than the maximum gainsetting, the amplifier draws more power than is necessary for therequired settling time.

SUMMARY

[0006] A sensor includes a pixel array, a read-out stage, and a gainstage that includes a differential amplifier with an adjustable gain.The differential amplifier may change its gain in response to themagnitude of a signal readout from the pixel array. The differentialamplifier includes an input transistor with an adjustabletransconductance. The transconductance of the input transistor isproportional to the power consumption of the input transistor. The inputtransistor includes two or more sets or parallel transistors, each setconnected to a different bias current supply. A transconductancecontroller can change the bias currents supplied to one or more sets ofparallel transistors and consequently change the transconductance, andpower consumption, of the input transistor. The transconductancecontroller can select a transconductance setting that is associated witha selected gain setting in order to more efficiently match the powerconsumption of the amplifier to its gain.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a block diagram of a sensor according to an embodiment.

[0008]FIG. 2 is a schematic diagram of a differential amplifier withvariable gain according to an embodiment.

[0009]FIG. 3 is a schematic diagram of the differential amplifier ofFIG. 2 in greater detail.

[0010]FIG. 4 is a block diagram of a bias current selection andgeneration circuit according to an embodiment.

[0011]FIG. 5 is a schematic diagram of a current multiplexer accordingto an embodiment.

[0012]FIG. 6 is a flowchart describing an operation for matching acurrent bias to a selected gain value according to an embodiment.

DETAILED DESCRIPTION

[0013] A sensor 100 according to an embodiment includes a pixel array102. The sensor 100 may be an active pixel sensor (APS), in which thepixel array includes a grid of individually addressable pixels 104arranged in rows and columns. Each pixel 104 includes a photodetector,such as a photogate, photodiode, or pinned photodiode. The photodetectorconverts light energy received in the form of photons into an electriccharge. This electric charge corresponds to an amount of light that thepixel 104 receives during an exposure to an image. The amount of lightreceived by each pixel in the array during exposure to the image is usedby the sensor 100 to produce a signal indicating a corresponding digitalimage.

[0014] After the exposure and a subsequent integration period, the pixelarray 102 is read out row-by-row for processing. The electric chargeheld in the pixel in each column in the selected row is output to asample-and-hold (S/H) unit 110 in a S/H block 112. The S/H unit 110 mayinclude a sampling switch and a holding capacitor to store the sampledanalog signal.

[0015] The sampled analog signals are passed from the S/H block 112 to again stage 120 before being sent to analog-to-digital converters (ADCs)in an ADC block 130 for conversion to digital signals. The ADCs may havea range of analog signals they can convert into discrete digital values.The analog signals generated by pixels exposed to very low levels oflight may fall below the lower limit of this range. The gain stage 120selects an appropriate gain setting to amplify such small analog signalsto values that are within a suitable range for the ADCs. The gain stage120 may have, for example, a minimum gain setting of 1 and a maximumgain setting of 8.

[0016] The gain stage 120 may include a class A differential amplifier200 with variable gain, as shown in FIG. 2. The differential amplifier200 has two input nodes 202, 204. The input voltages Vin_(n) and Vin_(p)applied to these nodes are equal in amplitude and 180° out of phase. Thedifferential amplifier also has two output nodes 206, 208. The outputvoltages Vout_(n) and Vout_(p) are equal in amplitude and 180° out ofphase.

[0017] The gain provided by the differential amplifier 200 may beadjusted by selecting an input capacitance and a feedback capacitance.The input capacitance may be set by selectively opening and closingswitches sw₀-sw₅, and the feedback capacitance may be set by selectivelyopening and closing switches sw₆-sw₇. Each switch sw₀-sw₇ is coupled toan associated capacitor C₀-C₇. Exemplary values for C₀ -C₇ are 12.5 fF,25 fF, 50 fF, 100 fF, 200 Ff, 400 fF, 100 fF, and 100 fF, respectively.The ratio of the input capacitance to the output capacitance determinesthe gain setting.

[0018] The power consumed by the amplifier increases with its gainbandwidth (GBW). The GBW of the amplifier is proportional to thetransconductance (g_(m)) of the input transistors in the amplifier, andis given by $\frac{gm}{2\pi \quad C},$

[0019] where C is the load capacitance. Since the transconductance isproportional to the bias current of the input transistor, the GBW may bevaried by changing the bias current of the input transistor.

[0020]FIG. 3 illustrates a differential amplifier 300 with variable gainand a variable GBW, which may be selected in response to the selectedgain in order to increase the efficiency of the amplifier. Rather thanhaving two input transistors for Vin_(n) and Vin_(p), respectively, theinput transistors are segmented into two sets of input transistors 302,304 and 312, 314. Each set of transistors is connected in parallel. Thebias current through the set of parallel transistors 302, 304 iscontrolled by bias transistor 320 with input terminal tail₁. The biascurrent through the set of parallel transistors 312, 314 is controlledby bias transistor 322 with input terminal tail₂.

[0021] The total bias current input to the differential amplifier 300 is2Ib₁+2Ib₂. The bias transistors 320, 322 form current mirrors. Each biastransistor controls the bias current through the two paralleltransistors to which it is connected. The tail₁ bias transistor 320 setsthe portion of the bias current flowing through each of the paralleltransistors 302, 304 to Ib₁, and the tail₂ bias transistor 322 sets theportion of the bias current flowing through each of the paralleltransistors 312, 314 to Ib₂.

[0022] The input transconductance, g_(m), and hence the GBW and powerconsumption, of the amplifier may be varied by varying the bias currentthrough one or both sets of parallel transistors (Ib₁ and/or Ib₂). In anembodiment, the bias current applied to terminal tail₂ is reduced forlower gain settings. When the bias current Ib₂ gets close to theoperating threshold for the parallel transistors 312, 314, i.e., thecurrent at which the transistors begin to turn off, the bias currentapplied to terminal tail₁ may then be reduced to further lower thetransconductance at the input of the differential amplifier 300.

[0023] As shown in FIG. 4, a gain decoder 402 selects a bias currentsetting in response to the gain setting. The gain decoder 402 controlstwo current multiplexers 410, 420. Each current multiplexer may includean array of ten 1 μA current sources 500-509, as shown in FIG. 5. Eachcurrent source 500-509 may be selected by closing a correspondingcontrol switch s<0>-s<9>. The total current output by a currentmultiplexer depends on the number of control switches selected by thegain decoder 402.

[0024] The currents 415, 425 output from the current multiplexers 410,420 are input to a bias generator 430. The bias generator 430 uses thesecurrents to generate bias voltages in response to the selected gainsetting and applies the bias voltages to terminals 350-355 (for bias₁,bias₂, bias₃, bias₄, tail₁, and tail₂, respectively). FIG. 6 is aschematic diagram of a bias generator circuit 600 according to anembodiment.

[0025] In an embodiment, the differential amplifier 300 may have threebias current settings; HIGH, MED, and LOW. The gain decoder 402 maydecode these three settings from the states of switches sw₃-sw₆. A HIGHsetting corresponds to a gain between 6 and 8, a MED setting correspondsto a gain between 3 and 6, and a LOW setting corresponds to a gainbetween 1 and 3. For the HIGH setting, all switches for both currentmultiplexers 410, 420 are closed, providing 100% of the available biascurrent. For the MED setting, all switches in the current multiplexer410 are closed, and switches s<0> and s<1> are closed in the currentmultiplexer 420, providing 60% of the available bias current. For theLOW setting, switches s<0> to s<3> are closed in the current multiplexer410, and all switches are open in the current multiplexer 420, providing20% of the available bias current.

[0026]FIG. 6 illustrates a flowchart describing a bias selection andgeneration operation 600 according to an embodiment. The flow of theoperation 600 is exemplary, and blocks in the flowchart may be skippedor performed in different order according to alternate embodiments.

[0027] A gain setting is selected (block 602) in response to theamplitude of the analog signal output from a pixel in a selected row.The switches sw₀-sw₇ are selectively opened and closed to produce theselected the gain setting (block 604). For example, in the presentembodiment, a gain of 1 is produced when all switches but switch sw₇ areopen, a gain of about 4 is produced when all switches are closed, and again of about 8 is produces when all switches but sw₆ are closed.

[0028] The gain decoder determines the bias current setting (HIGH, MED,or LOW) from the state of switches sw₃-sw₆ (block 606). The gain decodercontrols the current multiplexers 410, 420 to generate the currentappropriate for the gain setting and input the currents to the biasgenerator (block 608). The bias generator generates the appropriate biasvoltages for terminals 350-355 (bias₁, bias₂, bias₃, bias₄, tail₁, andtail₂) (block 610) and sets the bias current in the bias transistors320, 322 appropriate for the gain setting (block 612).

[0029] In alternate embodiments, the input transistors may be split intomore than two sets of parallel input transistors, each with anassociated bias transistor. This may provide more precise tuning of thebias current to the various gain settings. Each gain setting may beassociated with a distinct bias current setting to optimize powerconsumption in the amplifier for that gain setting.

[0030] With more sets of parallel input transistors, the bias currentmay be reduced in one set until the input transistors in that set beginto turn off, at which point the bias current in another set may bereduced. The use of multiple sets of parallel input transistors mayenable greater tuning of the bias current settings to the various gainsettings.

[0031] It may be desirable to provide a minimum amount of bias currentthrough all input transistors to prevent the input transistors fromturning completely OFF, which may produce unpredictable behavior in theamplifier.

[0032] An advantage of matching the GBW to a selected signal gain may bereduced power consumption of the amplifier. Another advantage may bereduced root mean square (RMS) voltage noise at the output of theamplifier. The total RMS voltage noise at the output of the amplifiermay be proportional to the root square of the amplifier's GBW. For aselected signal gain, matching the GBW to the signal gain selects thelowest GBW value for a given settling time requirement. This may produceless noise at the amplifier output compared to an amplifier that isdesigned for the worst-case gain setting (i.e., with no GBW matching tothe selected signal gain).

[0033] A number of embodiments have been described. Nevertheless, itwill be understood that various modifications may be made withoutdeparting from the spirit and scope of the invention. Accordingly, otherembodiments are within the scope of the following claims.

1. A method comprising: changing the gain of an amplifier in a gainstage of a sensor in response to a signal read out from a pixel array inthe sensor; and changing the power consumption of the amplifier in thegain stage in response to changing the gain.
 2. The method of claim 1,wherein said changing the power consumption comprises changing atransconductance of an input transistor in the amplifier.
 3. The methodof claim 1, wherein said changing the power consumption comprises:decreasing the power consumption in response to a decrease in the gain;and increasing the power consumption in response to an increase in thegain.
 4. The method of claim 1, further comprising: associating aplurality of power consumption settings with a plurality of gainsettings; selecting a gain setting from said plurality of gain settings;and selecting a power consumption setting associated with the selectedgain setting.
 5. The method of claim 4, wherein the gain setting isselected from eight gain settings.
 6. The method of claim 5, wherein thepower consumption setting is selected from three power consumptionsettings, each of three power consumption settings being associated witha different plurality of gain settings.
 7. The method of claim 4,wherein each of the plurality of gain settings is associated with adifferent one of the plurality of power consumption settings.
 8. Amethod comprising: selecting one of a plurality of gain settings inresponse to a signal read out from a pixel array in a sensor; generatingtwo or more bias currents having bias current values associated with theselected gain setting; and applying said two or more bias currents to aplurality of parallel transistors in an amplifier in a gain stage of thesensor in order to change the input transconductance of the amplifier.9. The method of claim 8, further comprising associated each of aplurality of input transconductance settings to a plurality of gainsettings, each input transconductance setting being associated with agiven set of bias current values.
 10. The method of claim 8, furthercomprising associating an input transconductance settings to each of aplurality of gain settings, each input transconductance setting beingassociated with a given set of bias current values.
 11. An apparatuscomprising: a gain stage for a sensor, said gain stage having adifferential amplifier including a gain selector operative to select oneof a plurality of gain settings in response to a signal from a pixelarray, an input transistor having a variable input transconductance, anda transconductance controller operative to select an inputtransconductance of the input transistor in response to a selected gainsetting.
 12. The apparatus of claim 11, wherein the transconductancecontroller is operative to select an input transconductance settingassociated with the selected gain setting from a plurality of inputtransconductance settings.
 13. The apparatus of claim 11, wherein theinput transistor comprises: a first plurality of parallel transistorsconnected to a first bias current supply; and a second plurality ofparallel transistors connected to a second bias current supply.
 14. Theapparatus of claim 13, wherein the transconductance controllercomprises: a bias current selector operative to select values for firstbias current and a second bias current associated with a selected gainsetting, and a bias current generator operative to generate a currenthaving the selected value for the first bias current and apply saidcurrent to the first bias current supply and to generate a currenthaving the selected value for the second bias current value and applysaid current to the second bias current supply.
 15. The apparatus ofclaim 14, wherein each set of current values produces a different inputtransconductance.
 16. The gain stage of claim 14, wherein the gainselector includes a plurality of switches and is operative to select adifferent set of switches for each of said plurality of gain settings.17. The gain stage of claim 16, wherein the bias current selector isoperative to select a set of current values in response to the switchesselected by the gain decoder.
 18. A sensor comprising: a pixel arraycomprising a plurality of pixels arranged in rows and columns; aread-out section operative to read out signals generated by pixels inthe pixel array; a gain stage having a differential amplifier includinga gain selector operative to set the differential amplifier to one of aplurality of gain settings in response to a pixel signal read out fromthe pixel array, an input transistor having an input transconductanceand including a first plurality of parallel transistors connected to afirst bias current supply and a second plurality of parallel transistorsconnected to a second bias current supply, and a transconductancecontroller operative to change the transconductance of the inputtransistor to match a selected gain setting by selectively applyingdifferent bias currents to at least one of said first and second biascurrent supplies for different gain settings.
 19. The sensor of claim18, wherein the transconductance controller comprises: a gain decoderoperative to select one or more bias current values in response to aselected gain response from a plurality of bias current values; and abias generator operative to generate and apply said one or more biascurrent values to at least one of the first and second bias currentsupplies.
 20. The sensor of claim 18, wherein the transconductancecontroller is operative to increase the transconductance of the inputtransistor in response to an increase in the gain of the differentialamplifier and to decrease the transconductance of the input transistorin response to a decrease in the gain of the differential amplifier. 21.The sensor of claim 18, wherein the sensor is an active pixel sensor(APS).
 22. A method comprising: changing the gain of an amplifier in again stage of a sensor in response to a signal read out from a pixelarray in the sensor; and changing a gain bandwidth (GBW) of theamplifier in the gain stage in response to changing the gain.
 23. Themethod of claim 22, wherein said changing the GBW comprises changing atransconductance of an input transistor in the amplifier.
 24. The methodof claim 23, wherein said changing the GBW comprises: decreasing the GBWin response to a decrease in the gain; and increasing the GBW inresponse to an increase in the gain.
 25. The method of claim 22, furthercomprising changing the root mean square (RMS) noise at an output of theamplifier in response to changing the GBW.
 26. The method of claim 25,wherein said changing the RMS noise comprises: decreasing the RMS noisein response to a decrease in the GBW; and increasing the RMS noise inresponse to an increase in the GBW.